陈荣梅先后于2012年和2017年在清华大学取得本科和博士学位，现在法国国家科学院从事博士后研究。主要从事集成电路的辐射效应，碳纳米管互连线和晶体管的集成工艺、物理分析和电路建模与设计的研究。截止到目前在IEEE Transactions on Nuclear Science, Microelectronics, IEEE Transactions on Nanotechnology 等知名期刊上发表了近十篇论文，其中一作六篇。还有三篇文章在IEEE Transactions on Electron Devices上审稿。多次参加国际知名会议，并在集成电路辐射效应顶级会议NSREC和RADECS上做了数次口头报告，研究成果得到国际知名专家和同行的高度认可。
Contents
Chapter 1Introduction
1.1Research Background
1.2Radiation Environment in Space
1.3Radiation Effects of Logic Circuit
1.3.1SingleEvent Effect and TID Effect
1.3.2SingleEvent Effect of Logic Circuit
1.4State of the Art of the Research
1.4.1SEU Propagation Principle in NanoLogic
Circuit
1.4.2Impact of Layout Structure on SET of
NanoLogic Circuit
1.4.3Impact of TIE Effect on SEE of NanoLogic
Circuit
1.4.4Impact of Temperature on SEE of NanoLogic
Circuit
1.5Rearch Content and Goals of This Book
Chapter 2Research of SEU Propagation Principle in NanoLogic Circuit
2.1Introduction
2.2Analysis and Simulation Demonstration of SEU
Propagation Model of Loigic Circuit
2.2.1Analysis of Current SEU Propagation Model
2.2.2Simulation Demonstration of Current SEU
Propagation Model
2.2.3Proposed SEU Propagation Model
2.3Experimental Demonstration of Proposed SEU
Propagation Model
2.3.1Circuit Design and Methodology
2.3.2Experimental Restuls and Discussion
2.4Applications of the Proposed SEU Propagation Model
2.4.1Hardening Strategies for FlipFlop SEU
Soft Error
2.4.2SEE Soft Errors Dynamic Cross Section
Evaluation for Logic Circuit
2.5SingleEvent Soft Error Propagation Impacting Factors
2.5.1Circuit Design
2.5.2Impact from Combinational Logic Delay Time
2.5.3Impact from Injecting Particle LET
2.5.4Impact from SEU Resistent Capability of
FlipFlop
2.5.5SingleEvent Soft Error Cross Section Prediction
2.6Conclusion
Chapter 3Research of the Impact of Layout Structure on SET of
NanoLogic Circuit
3.1Introduction
3.2Circuit Design and Experimental Methodology
3.2.1Circuit Design
3.2.2Experimental Methodology
3.3Experimental Results and Discussion
3.3.1Clibration of SET Pulse Width Measurement
Resolution and LowerLimit
3.3.2Calibration of SET Pulse Width Broadening
Factor
3.3.3Heavy Ion Vertical Injection Experimental
Results and Analysis
3.3.4Heavy Ion Tilted Injection Experimental
Results and Analysis
3.3.5Pulsed Laser Experimental Results and Analysis
3.3.6Comparions and Discussion
3.4Conclusion
Chapter 4Research of Impact of TIE Effect on SET of
NanoLogic Circuit
4.1Introduction
4.2Experimental Methodology
4.3TID Induced Static Leakage Current Variation
4.4Impact of TID on SEU of Logic Circuit
4.4.1Experimental Results
4.4.2Results Discussion
4.5Impact of TID on SET of Logic Circuit
4.5.1Experimental Results
4.5.2Results Discussion
4.6Conclusion
Chapter 5Research of the Impact of Temperature on SEU of
NanoLogic Circuit
5.1Introduction
5.2Circuit Design and Experimental Methodology
5.2.1Circuit Design
5.2.2Experimental Methodology
5.3Impact of Temperature on SEU of NanoLogic Circuit
5.3.1Experimental Results
5.3.2Results Discussion
5.4Impact of Temperature on SET of NanoLogic Circuit
5.4.1Experimental Results
5.4.2Results Discussion
5.5Conclusion
Chapter 6Conclusion and Perspectives
6.1Conclusion of This Book
6.2Innovations in This Book
6.3Interesting Future Research
References
Related Publications During the PhD
Related Research Achievements
Acknowledgement
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