《EDA 技术与 Verilog HDL （英文版）》 systematically introduces EDA technology and Verilog HDL. It well combines the basic knowledge, programming skills and practical methods of EDA technology and Verilog HDL with the actual engineering development technologies. According to the regulations and requirements of the classroom teaching and experimental operation in universities and colleges, and with the aim of enhancing the practical engineering design ability and independent innovation capability of students, the authors reasonably arrange the content of the whole book. The book is divided into seven parts： overview of EDA technology, syntax knowledge and practical technology of Verilog HDL, detailed usage of Quartus and IP module, design technology of finite state machine, 1632-bit practical CPU design technology and innovative practical project, ModelSim-based Test Bench simulation technology and a large number of practical system design examples. Apart from a few chapters and sections, most of the chapters arrange the corresponding exercises and a large number of highly targeted experiments and design projects. All of the Verilog HDL examples enumerated in the book have passed through the compiling or hardware testing. 《EDA 技术与 Verilog HDL （英文版）》 can be used as the textbook or reference book for the subjects of electronics, computer, and automation, and can provide teaching PPT courseware, experimental source programs and demonstration videos and so on.
目錄：
Chapter 1 Introduction1
1.1 EDA Technology1
1.2 Object for EDA Technology3
1.3 Common Hardware Description Languages 5
1.4 Advantages of EDA Technology7
1.5 Development Flow for FPGA and CPLD9
1.5.1 Design Input9
1.5.2 Synthesis 10
1.5.3 Fit Place and Route13
1.5.4 Simulation13
1.5.5 RTL Description14
1.6 Programmable Logic Devices14
1.6.1 Classification of PLD15
1.6.2 Programming Principle of PROM16
1.6.3 GAL18
1.7 Structure and Programming Principle of CPLD20
1.8 Structure and Working Principle of FPGA23
1.8.1 Logical Structure of LUT23
1.8.2 Structural Principle of Cyclone 4E Series Devices 24
1.8.3 FPGA Device with Embedded Flash27
1.8.4 Major Manufacturers of FPGA27
1.9 Hardware Testing Technology28
1.9.1 Internal Logic Test28
1.9.2 JTAG Boundary Scan Test28
1.10 Programming and Configuration29
1.11 Quartus30
1.12 IP Core 32
1.13 Major EDA Software Companies33
1.14 Development Trend of EDA34
Exercises 36
Chapter 2 Program Structure and Data Type37
2.1 Verilog Program Structure37
2.1.1 Expression of Verilog Module38
2.1.2 Signal Name and Mode of Verilog Module Port 39
2.1.3 Definition of Verilog Signal Type40
2.1.4 Function Description of Verilog Module41
2.2 Data Types of Verilog41
2.2.1 Net Type41
2.2.2 Definition of Wire Type Variable41
2.2.3 Register Type42
2.2.4 Definition of Register Type Variable42
2.2.5 Definition of Integer Type Variable43
2.2.6 Memory Type44
2.3 Verilog Syntax Rules45
2.3.1 Four Logical States in Verilog46
2.3.2 Digital Expression Forms of Verilog46
2.3.3 Expression of Data Type47
2.3.4 Constant47
2.3.5 Identifiers, Keywords, and Other Syntax Rules 49
2.3.6 Usage of parameter and localparam 51
Exercises 51
Chapter 3 Behavioral Statements53
3.1 Procedural Statement53
3.1.1 always Statement54
3.1.2 The Application of always Statement in D flip-flop Design55
3.1.3 The Application of Multi-Process and Asynchronous Sequential Circuit
Design56
3.1.4 Verilog Expression of Simple Up Counter 57
3.1.5 initial Statement58
3.2 Block Statement60
3.3 case Conditional Statement61
3.4 if Conditional Statement62
3.4.1 General Expression of if Statement62
3.4.2 Combinational Circuit Design Based on if Statement63
3.4.3 Sequential Circuit Design Based on if Statement 65
3.4.4 Design of DFF with Asynchronous Reset and Clock Enable67
3.4.5 Design of DFF with Synchronous Reset68
3.4.6 Design of Latches with Clear69
3.4.7 Characteristics and Rules of Clock Procedural Statement70
3.4.8 Practical Up Counter Design72
3.4.9 Shift Register Design with Synchronized Preset Function74
3.4.10 Conditional Instructions in if Statements 76
3.5 Statement of Procedural Assignment77
3.6 Loop Statement78
3.6.1 for Statement78
3.6.2 while Statement79
3.6.3 repeat Statement81
3.6.4 forever Statement81
3.7 task and function Statements81
Exercises 84
Chapter 4 FPGA Hardware Implementation86
4.1 Code Editing Input and System Compilation86
4.1.1 Design File Edit and Input86
4.1.2 Creating a Project87
4.1.3 Constraint Item Setting89
4.1.4 Comprehensive Synthesis and Compilation 90
4.1.5 Application of RTL Viewer92
4.2 Timing Simulation93
4.3 Hardware Testing96
4.3.1 Pin Assignment97
4.3.2 Compiled File Download 99
4.3.3 Indirect Programming of Configuration Chip through JTAG100
4.3.4 USB-Blaster Driver Installation 102
4.4 Circuit Schematic Design Flow 102
4.4.1 Half-adder Design 102
4.4.2 Top-level Design of Full-adder104
4.4.3 Timing Simulation and Hardware Testing of Full Adders105
4.5 Pin Assignment Using Attributes107
4.6 Usage of SignalTap II 108
4.7 Trigger Signal Edit of SignalTap II 114
4.8 Installation of Quartus II 13.1114
Exercises 119
Labs and Designs120
Lab 4-1 Multiplexer Design 120
Lab 4-2 Hexadecimal 7-segment Digital Display Decoder Design120
Lab 4-3 8-bit Hardware Multiplier Design122
Lab 4-4 Design of a Digital Frequency Meter Using Macro Modules122
Lab 4-5 Counter Design127
Lab 4-6 Digital Scan and Display Circuit Design 128
Lab 4-7 Half-integer and Odd Frequency Divider Design128
Chapter 5 Operators and Structural Description Statement131
5.1 Operators of Operation 131
5.1.1 Bit Logical Operator131
5.1.2 Logical Operator 132
5.1.3 Arithmetical Operator132
5.1.4 Relational Operator 134
5.1.5 Example of Adder based on BCD Code 135
5.1.6 Contraction Operator 136
5.1.7 Parallel Connection Operator 136
5.1.8 Shift Operator137
5.1.9 Example of Shift Operator 137
5.1.10 Conditional Operator 138
5.2 Continuous Assignment Statement139
5.3 Instantiation Statement140
5.3.1 Half-adder Design 140
5.3.2 Full-adder Design141
5.3.3 Verilog Instantiation Statement and Its Usage 142
5.4 Application of Parameter Transmission Statement 144
5.5 Structural Description with Library Component 145
5.6 Compiling Directive Statement 147
5.6.1 Macro Definition Statement 147
5.6.2 File Inclusive Statement, ''include148
5.6.3 Conditional Compilation Statement, ''ifdef, ''else, ''endif 149
5.7 Application of Attribute of Keep 150
5.8 Usage of SingalProbe152
Exercises 154
Labs and Designs157
Lab 5-1 High-speed Hardware Divider Design 157
Lab 5-2 Design of Various Types of Shift Registers 158
Lab 5-3 Verilog Code-based Frequency Meter Design 158
Lab 5-4 8-bit Adder Design159
Lab 5-5 VGA Displayer Control Circuit Design 160
Chapter 6 The Usage of LPM Macro Module165
6.1 The Example of Invoking Macro Module of Counter 165
6.1.1 The Invoking of the Text Code of the Counter LPM Module165
6.1.2 Application of LPM Counter Code and Parameter Transmission Statement . 167
6.1.3 Project Creation and Simulation Testing169
6.2 Example of Building Attribute Control Multiplier169
6.3 Usage of Macro Block of LPM_RAM171
6.3.1 Initialization File and Its Generation172
6.3.2 Invoking LPM_RAM by Schematic Diagram Method174
6.3.3 Test LPM_RAM176
6.3.4 Expression of Memory Initialization File Loading of Verilog Code Description . 177
6.3.5 Structure Control of Memory Design178
6.4 Usage Examples of LPM_ROM180
6.4.1 Design of Simple Sinusoidal Signal Generator . 180
6.4.2 Hardware Implementation and Testing of Sinusoidal Signal Generator . 182
6.5 Application of In-System Memory Content Editor 183
6.6 Invoke of Embedded PLL of LPM185
6.6.1 Building Embedded PLL Component185
6.6.2 PLL Test . 188
6.7 The Usage of In-System Sources and Probes Editor 188
6.8 Principle and Application of DDS 191
6.8.1 Principle of DDS 192
6.8.2 Example of DDS Signal Generator194
Exercises 195
Labs and Designs196
Lab 6-1 Look-up Table based Hardware Operator Design196
Lab 6-2 Sinusoidal Signal Generator Design197
Lab 6-3 Design of Simple Data Acquisition System 197
Lab 6-4 DDS-based Sinusoidal Signal Generator Design 198
Lab 6-5 Phase-shifted Signal Generator Design 199
Lab 6-6 Amplitude-Modulated Signal Generator Design200
Lab 6-7 Hardware-Based De-jitter Circuit Design200
Chapter 7 Deep Understanding of Verilog HDL203
7.1 Two Types of Assignment Statements in Process 203
7.1.1 Blocking Assignment with Unspecified Time-delay203
7.1.2 Blocking Assignment with Specified Time-delay 204
7.1.3 Non-blocking Assignment with Unspecified Time-delay205
7.1.4 Non-blocking Assignment with Specified Time-delay207
7.1.5 Deep Understanding of the Features of Blocking and Non-blocking
Assignments209
7.1.6 Further Discussion of Different Initialization Ways211
7.2 Discussion of Procedural Statement213
7.2.1 Conclusion of Procedural Statement Application 213
7.2.2 Relationship between Incomplete Conditional Statement and Sequential
Circuit214
7.3 Design of Three-state and Bidirectional Port217
7.3.1 Design of Three-state Control Circuit217
7.3.2 Design of Bidirectional Port. 217
7.3.3 Design of Three-state Bus Control Circuit 220
7.4 Resource Optimization 222
7.4.1 Resource Sharing 223
7.4.2 Logic Optimization 224
7.4.3 Serialization225
7.5 Speed Optimization226
Exercises 229
Labs and Designs230
Lab 7-1 Design of the Signal Detection Circuit of 44 Array Keyboard230
Lab 7-2 Design of Direct Current Motor-based Synthesized Measurement and
Control System 232
Lab 7-3 Design of Control Module of VGA-based Simple Image Displaying 234
Lab 7-4 Design of Hardware-based Music Performing Circuit235
Lab 7-5 Design of Electronic Organ Circuit based on PS2 Keyboard Control
Model240
Chapter 8 Design Technology of State Machine 243
8.1 General Form of Verilog State Machine243
8.1.1 Characteristics and Advantages of State Machine 243
8.1.2 General Structure of State Machine245
8.1.3 Initial Control and Expression249
8.2 Moore-type State Machine250
8.2.1 State Machine with Multiprocess Structure251
8.2.2 Sequence Detector and Its State Machine Design 255
8.3 Mealy-type State Machine257
8.4 State Machine with Different Coding Types260
8.4.1 Direct Output Coding260
8.4.2 Defining the State Coding with the Use of Macro Definition Statement 262
8.4.3 Sequential Coding 263
8.4.4 One-hot Coding264
8.4.5 Setting of State Coding265
8.5 Design of Safe State Machine266
8.5.1 State Guiding Method 267
8.5.2 Monitoring Method of State Coding268
8.5.3 Auto-generation of Safe State Machine with the Use of EDA Tool 269
Exercises 269
Labs and Designs270
Lab 8-1 Design of Sequence Detector 270
Lab 8-2 Design of ADC Sampling Control Circuit 270
Lab 8-3 Design of Intelligent and Logical Pen with Five Functions272
Lab 8-4 Design of Data Acquisition Module274
Chapter 9 1632-bit CPU Innovation Design276
9.1 Architecture and Characteristics of KX9016276
9.2 Design of KX9016 Basic Hardware System280
9.2.1 Module of One-step Beat Generation 280
9.2.2 ALU Module281
9.2.3 Comparator Module281
9.2.4 Basic Register and Register Array282
9.2.5 Shifting Register Module 286
9.2.6 Program and Data Memory Module286
9.3 Design of KX9016v1 Instruction System287
9.3.1 Instruction Format287
9.3.2 Instruction Operation Code289
9.3.3 Example of Software Program Design290
9.3.4 Design of KX9016 Controller292
9.3.5 Example of Instruction Design297
9.4 Timing Simulation and Hardware Testing of KX9016298
9.4.1 Timing Simulation and Waveform Analysis of Instruction Execution 299
9.4.2 Hardware Testing of CPU Operation Condition 301
9.5 Examples of Application Program Design and System Optimization of KX9016 304
9.5.1 Multiplication Algorithm and Its Hardware Implementation 304
9.5.2 Division Algorithm and Its Hardware Implementation306
9.5.3 Optimization of KX9016v1 Hardware System307
9.6 Design of 32-bit RISC-V Processor309
9.6.1 RISC-V Basic Structure and Basic Integer Instruction Set RV32I 309
9.6.2 2-bit Multiplication Instruction Set RV32M312
9.6.3 16-bit Compressed Instruction Set RVC 313
Exercises 314
Labs and Designs314
Lab 9-1 Comprehensive Experiment of 16-bit CPU Design314
Lab 9-2 Experiment of New Instruction Design and Program Testing 315
Lab 9-3 Optimization Design and Innovation of 16-bit CPU. 316
Chapter 10 Verilog HDL Simulation318
10.1 Verilog HDL Simulation Flow319
10.2 Example of Verilog Test Bench322
10.3 Testing Flow of Verilog Test Bench324
10.4 Verilog System Tasks and System Functions327
10.4.1 System Tasks and System Functions327
10.4.2 Precompiled Statements333
10.5 Delay Model334
10.5.1 # Delay and Gate Delay334
10.5.2 Delay Description Block335
10.6 Other Simulation Statements335
10.6.1 fork-join Block Statements336
10.6.2 wait Statement337
10.6.3 force, release Statement337
10.6.4 deassign Statement338
10.7 Generation of Simulation Excitation Signals338
10.8 Digital System Simulation339
Exercises 340
Labs and Designs341
Lab 10-1 Simulating the Test Bench of Counter on ModelSim341
Lab 10-2 Design and Simulate a 16-Bit accumulator on ModelSim341
Appendix A Development Systems and Softwares for EDA342
A.1 KX-CDS Series EDASOPC System343
A.1.1 Modular Independent Innovation Experimental Design Structure . 344
A.1.2 Multifunctional Reconfigurable High-Efficiency Experimental Control
System345
A.1.3 FPGA Core Board of Different Functional Types 345
A.2 Some Expansion Modules for Experiments348
A.3 Usage of MIF file generator350
A.4 Reference Table for Extending Core Board FPGA to KX-CDS System352
A.5 Part of the Experimental Circuit Diagram with Switchable Multifunctional
Reconfigurable Structure354
A.6 HX1006A and Pin Assignment Tool357
References359
內容試閱：
This book is an English version of EDA Technology and Verilog HDL published by Tsinghua University Press.
Based on the great practical value of EDA technology in engineering domain and significant importance on the cultivation of practical ability and innovative awareness in the teaching of EDA, the characteristics of the book are mainly reflected in the following two aspects.
1. Great attention on the cultivation of practical ability and innovative ability
In most chapters, the highly targeted experiments and design projects are arranged, which make the students digest and strengthen the teaching content and effect of each chapter through experiments, and possibly link closely the theoretical knowledge with practice and independent design from the beginning of study.
The book includes dozens of experiments and the related design projects. These projects relate to EDA tool software of various types, broad technology areas, intensive and targeted knowledge dabbling and independent innovation awareness with good revelation. Same as the examples in the book, all of the experimental projects pass through the simulation test of EDA tools and hardware verification of FPGA platform. In addition to the detailed requirements on experimental objectives, experimental principles and experimental reports, each experimental project has 2～5 subprojects or subtasks. They are usually divided into： the first level experiments are the verification experiments related to the content elaborated in the chapter, and usually provide detailed and verified design source programs and experimental methods. The students only need to input the code to the computer, compile and simulate according to the requirements and implement them on the experimental system, which make the students have preliminary perceptual knowledge and enhance the efficiency of the experiments. The second level experimental task is to make some improvement and exertion based on the last experiment.
The third level experiment is usually to propose the requirements and tasks of independent design.
The fourth and fifth experimental level is to raise the requirements on independent innovation design in the case of only giving some hints. Therefore, teachers can arrange different levels of experimental projects with different tasks, according to the course hours, requirements on
teaching experiments and different student objects.
2. Great attention on the combination of flexibility and completeness in teaching
material selection
The structural features of the textbook determine that the number of teaching hours is very flexible, which can be long or short, depending on the specific major characteristics, course orientation and the degree of early education of learners. The course hours are approximately 30～54. Considering the characteristics of the EDA technology course and the text book, the concrete teaching can be extensive, in which most of the content, particularly the practical projects, allow students to access information, raise questions, solve problems, and even innovate and create by themselves. The teacher only needs to be an enlightener, guider, encourager and examiner and appraiser of the students achievements. In most cases, the teaching process needs to be finished when the meaning has been conveyed, and there is no need to stick to details and be well-rounded. But there is a principle that the number of scheduled experimental hours should
be the more the better.
In fact, the number of hours in any course is always limited. To effectively increase the time of the practice and self-design of students, a teaching reform measure of Tsinghua University can be used for reference. That is, each of the undergraduate students of the electronics department gets an FPGA development board from entrance, and can use the board from the first year of undergraduate study to the end of postgraduate study. This is because EDA technology itself is a course that takes all the lab exercises and designs back home.
Our university has also basically adopted this measure for this course. That is, every student in the EDA course can borrow a set of EDA experimental board, so that they can utilize their own computers to complete the self-design projects in their spare time and strengthen the learning effect. The practice has indicated that, this arrangement has extended the experimental hours effectively and the teaching effect is naturally remarkable.
We suggest encouraging the students to utilize their spare time to learn all the content of the book as much as possible, master all the EDA tools and software and related development tools introduced in this book, and complete the experiments and design tasks of this book as much as possible. We can even refer to the requirements of the textbook, arrange the related innovation design competitions, further stimulate students enthusiasm and initiative in learning and strengthen the training of their manipulative ability and independent innovation ability.
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